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64-Bit Burst Transfer
When operating in 64-bit mode ( Figure 6-19 through Figure 6-21 on page 70 ), the backend protocol is similar to that
for 32-bit operation. The main differences are that the data bus width increases to 64 bits and four additional write
strobes are provided along with four additional read byte strobes to support byte operations. Also, the address increments
by eight rather than by four after each data transfer.
cycle
0
1
2
3
4
5
6
7
8
9
clk
framen
req64n
ack64n
cben[7:0]
F6
00
ad[63:0]
ADDR
1,0
3,2
5,4
7,6
par
par64
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
xfer_64bit
rd_cyc
rd_stb_out
rd_stb_in
0
mem_add[15:0]
mem_data_in[63:0]
0000
1,0
0008
3,2
0010
5,4
0018
7,6
0020
9,8
0028
B,A
rd_sync
Figure 6-19 · 64-Bit Burst Read Cycle (RD_SYNC = 0)
68
v4.0
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